CD4078 NOR/OR Gate provides the system designer with direct implementation of the positive-logic 8-input NOR and OR functions and supplements the existing family of CMOS gates.
The CD4078 types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shink small-outline packages (PW and PWR suffixes).
Features:-
- Medium-Speed Operation:
tPHL, tPLH = 75 ns (typ.) at VDD = 10 V - Buffered inputs and output
- 5-V, 10-V, and 15-V parametric ratings
- Standardized symmetrical output characteristics
- 100% tested for quiescent current at 20 V
- Maximum input current of 1 µA at 28 V over full package-temperature range:
100 nA at 18 V and 25°C - Noise margin (over full package-temperature range):
- 1 V at VDD = 5 V
- 2 V at VDD = 10 V
- 2.5 V at VDD = 15 V
- Meets all requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”
Specifications:-
Parameter | Specification |
Part number | CD4078B |
Technology Family | CD4000 |
VCC (Min) (V) | 3 |
VCC (Max) (V) | 18 |
Channels (#) | 1 |
Inputs per channel | 8 |
Output type | Push-Pull |
Features | Standard Speed (tpd > 50ns) |
Data rate (Max) (Mbps) | 8 |
IOL (Max) (mA) | 6.8 |
IOH (Max) (mA) | -6.8 |
Package size: mm2:W x L (PKG) | 14PDIP: 181 mm2: 9.4 x 19.3 (PDIP|14) |
Rating | See Data Sheet |
Operating temperature range (C) | -55 to 125 |
Package Group | PDIP|14 |
* product image for illustration purposes only. actual product may vary.
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